The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to testing and defect analysis of semiconductor dice involving logic state mapping.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
A by-product of such high-density and high functionality is an increased demand for products employing these microprocessors and devices for use in numerous applications. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased. Such devices often require manufacturing processes that are highly complex and expensive.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that an individual die is functional, it is also important to ensure that batches of dice perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. Directly accessing the circuitry is difficult for several reasons. For instance, in flip-chip type dice, transistors and other circuitry are located in a very thin epitaxially grown silicon layer in a circuit side of the die. The circuit side of the die is arranged face-down on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the die.
One particular type of semiconductor device structure that presents unique challenges to back side circuit analysis is silicon-on-insulator (SOI) structure. SOI involves forming an insulator, such as an oxide, over bulk silicon in the back side of a semiconductor device. A thin layer of silicon is formed on top of the insulator, and is used to form circuitry over the insulator. The resulting SOI structure exhibits benefits including reduced switch capacitance, which leads to faster operation. Direct access to circuitry for analysis of SOI structure, however, involves milling through the oxide. The milling process can damage circuitry or other structure in the device. Such damage can alter the characteristics of the device and render the analysis inaccurate. In addition, the milling process can be time-consuming, difficult to control, and thus expensive.
Another challenge to analysis of integrated circuit dice is correlating a response to a particular portion or portions of circuitry. Often, when dice are tested, the source of a particular detected response is difficult to determine. As integrated circuit-dice are scaled smaller, individual circuit elements are placed closer together. When a response is obtained from a die, the close placement makes it difficult to determine exactly where the response came from. In addition, responses generated are often the result of action at another circuit portion electrically coupled to the response-generating circuit. In this instance it is difficult to determine where the response was actually generated in relation to where it is detected.
The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits are impediments to the growth and improvement of semiconductor technologies involving SOI structure.
The present invention is directed to a method and system for analyzing a semiconductor die having silicon-on-insulator (SOI) structure in a manner that overcomes the above-discussed impediments. The die includes a back side opposite circuitry in a circuit side, and the die analysis involves electrically coupling to the circuitry with mapping of logic states in the die circuitry. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor die having SOI structure and a back side opposite circuitry in a circuit side is analyzed. The back side of the semiconductor die is thinned, either prior to or as part of the present analysis. The die is operated in a manner that causes circuitry in the die to take on a selected logic state. A probe is used to scan the thinned back side of the die using the insulator portion of the SOI structure as a dielectric to couple to the circuitry. The probe generates a response from the die that is detected and used to detect a logic state of circuitry in the die. The logic state is then mapped to a particular portion of the circuitry. In this manner, the logic state of selected circuitry in the die can be detected under various operating conditions.
According to another example embodiment of the present invention, a system is adapted to analyze a semiconductor die having silicon-on-insulator (SOI) structure and a back side opposite circuitry in a circuit side. A power supply is adapted to operate the die at a selected logic state. A probe is arranged over the back side and adapted to scan the die using the insulator portion of the SOI structure as a dielectric and to detect a response from the scanning. An analysis device is adapted to use the response to detect a logic state of the circuitry and map the logic state to a particular portion of the circuitry.